UVM Introduction

UVM stands for Universal Verification Methodology. But to answer what exactly means and it's so much important, keep reading this blog and all related articles.

WHAT IS UVM?

UVM is a library of classes written in System verilog which implements the building blocks of a verification environment. It's an open source library is maintained by industry standard body "Accellera". It's the latest standardized methodology for verifying digital hardware designs and System on Chips (SoCs) in semiconductor related companies.

To understand it much simpler, UVM is a library of classes, set of guidelines and best practices on how to create a verification environment to verify any digital design. it covers everything from how to create an environment, running simulation and checking results.

WHAT WAS USED BEFORE UVM?

Before UVM became so popular among verification engineers, there were several other verification techniques and methodologies used to verify digital hardware designs. These techniques evolved over time to address the complexity to digital design, focus towards automation and reusability of same verification environment for multiple projects. Some of the known verification methodologies used before UVM includes:

1. Directed Testing: In early days of digital verification, verification engineers used to create direct testcases to verify the functionality of a design. The biggest drawbacks of this approach was:

• If the understanding of design is incorrect, it results in missing the correct scenario verification.

• The corner cases cannot be identified and tested with this approach.

• No reusability. This type of environment and testcases cannot be reused for other projects to save time.

• This type of approach cannot handle complex design verification.

2. VHDL/ Verilog/ System verilog Testbenches: With the evolution of hardware languages, creating testbenches and test environments using VHDL, Verilog, System verilog also became quite popular. Engineers used to create verification environment with these languages and write dedicated testcases to verify the functionality of a digital design. The result can be seen as a waveform in multiple industry simulators.

Few problems with this approach was:

• Reusability was still not answered. The environment is not much reusable for different projects.

• Complex design verification was not easily handled by this approach

• There was not standard approach or methodology. For same design, multiple verification engineers can create different testing environments as per their knowledge and it creates problems and consumes time to understand the testing environment from engineer to engineer

• Lots and lots of code has to be written to automate basic functionalities. Examples can be like deep copy, complex comparing etc.

3. Open Verification Methodology (OVM): OVM was introduced in 2008 and it was system verilog based verification methodology, guidelines and best practices to create reusable verification environments and to verify complex designs. It was developed by Mentor graphics (now part of Siemens) and later became an Accellera standard.

UVM was released in 2011 and it is an enhanced and improved version of OVM. As UVM is more advanced and standardized methodology, the verification community gradually shifted towards adopting UVM.

WHAT IMPROVEMENTS UVM BROUGHT OVER OVM?

Some of the major improvements which UVM brought over OVM are:

1. Base class library: UVM introduced a new base class library which is a foundation of UVM. This base class library includes reusable base classes for different verification components (discussed later in the course) like sequencer, driver, monitor etc. It simplified the task of creating a verification environment, directly by using these base classes and promoting reusability.

2. Sequences: UVM first introduced the concept of sequences to represent transaction level stimulus generation. To understand this in simple languages, rather than dealing with individual signals like address, data, read etc. A transaction or packet class is created which encapsulates these signals like address, data, read etc. So the sequence defines the scenario to be verified in terms of transaction class or packet like eg. send 100 packets of write to 100 consecutive addresses with random data. Sequences provide more structured way to model stimulus.

3. Phasing Mechanism: Phasing is one of the most important feature of UVM. Phasing allows a structured and synchronized approach to a verification task. This ensures various components of testbench proceeds through different phases of the testbench lifecycle systematically.

4. Configuration database: UVM introduced a global configuration database that allows easy sharing of configuration data among different components in the testbench. This simplifies parameterization and promotes configurability and reusability. In simpler terms, you can set variables from top level classes. This feature is explained better in upcoming blogs.

5. Transaction-Level Modeling TLM: UVM provides a TLM layer, which allows to communicate between different components of Testbench using ports, exports and imports of TLM.

6. Factory: UVM introduced a factory layer, enabling more flexible and efficient creation and configuration of verification components. A parent class can be overridden by child class without changing the code in Verification environment.

7. Improved Reporting and Messaging: UVM introduced improved reporting and messaging features, making it easier to understand and debug verification issues by providing more detailed and customizable messages. There are level of switches via which you can control how many messages or verbosity of messages in log files to aid debug. The print messages can pin point from which line of code or which component called this print.

8. Component Hierarchies: UVM introduced better support for hierarchical testbenches and testbench reusability, allowing verification engineers to organize and manage the complexity of larger projects effectively. This makes it a systematic approach.

9. Enhanced RAL (Register Abstraction Layer): UVM refined the RAL to provide a more robust and efficient way of modeling, accessing and verifying design registers.

PREREQUISITES FOR LEARNING UVM

UVM is a library of classes written in System verilog. To understand it much better, you should have a basic to good level of understanding of System verilog and C++ OOPs concepts.